1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit which generates an output clock synchronized with a reference clock and maintaining a phase relationship to the reference clock. More particularly, it relates to a DLL circuit which makes it possible to accurately generate an output clock for a short time even if the reference clock is changed by noise occurrence, and a memory device in which the DLL circuit is built.
2. Description of the Related Art
A PLL or DLL circuit is used as a self-timing control circuit (STC) which generates an internal clock in synchronism with an external reference clock, for example. This DLL circuit is well-known as a circuit which generates an output clock synchronized with a reference clock supplied from the external device and maintaining the prescribed phase relationship as usual.
In recent years, in a synchronous memory device, such as a synchronous DRAM (SDRAM) which performs high-speed operations, the DLL circuit is provided inside, and an internal clock which maintains the prescribed phase relation ship in synchronism with a reference clock supplied from a memory controller side, for example, an internal clock synchronized by a same phase or a prescribed angle from the reference clock is generated. The internal clock is employed to control the timing of reading out an output, thereby controlling the timing of reading out an output at the reference clock supplied by the memory controller side and making the high-speed operations in the SDRAM possible.
A loop type of DLL circuit comprising a variable delay circuit which generates a delay clock by giving a delay to a reference clock, a phase comparator which detects a phase difference between the reference clock and the delay clock, and a delay control circuit which generates a delay control signal such that there is no phase difference between the two supplied clocks.
This DLL circuit is controlled so as to keep the locked status where there is no phase difference with the reference and delay clocks. Therefore, even if some small changes occur on the reference clock by noises, a clock which is phase synchronized to the reference clock supplied for a prescribed long period can be generated. However, the delay control signal is generated, judging whether or not the phases are coincident every time a reference clock is supplied, and therefore, it takes long time to achieve to the locked status.
On the other hand, another DLL circuit is an non-loop type DLL circuit comprising a variable delay circuit which generates an targeted output clock by giving a delay to a reference clock and a clock cycle measurement section which generates a delay control signal suitable to the length of clock cycle. This circuit does not require long time to achieve to the locked status, not similarly to the above-described loop type DLL circuit.
However, since a non-loop type DLL circuit measures a clock cycle of reference clock supplied actually, if the reference clock is changed by an unexpectedly generated noise when measuring the cycle, and a clock cycle different from a normal cycle is detected, a delay control signals may be generated according to the wrong clock cycle. It is general to perform clock cycle measurement operations on this DLL circuit in every cycles of a plurality of reference clocks. Therefore, if a delay control signal according to the wrong clock cycle is generated, an output clock will be generated at the wrong timing until coming to the subsequent clock cycle measurement.